At present, digital to analog converters have been widely applied in various fields. For example, in a communications base station, both a receive channel and a feedback channel generally need a high-speed and high-precision digital to analog converter.
A level shifter used in a digital to analog converter in the prior art is shown in FIG. 1, and includes a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a fourth field effect transistor M4, a first capacitor C1, a second capacitor C2, and a phase inverter IVN, where the first field effect transistor M1, the second field effect transistor M2, and the fourth field effect transistor M4 are N-type field effect transistors, and the third field effect transistor M3 is a P-type field effect transistor; a source of the first field effect transistor M1 is connected to a source of the second field effect transistor M2, and a connecting end after the connection is connected to a direct current power supply, where the direct current power supply is a working power supply of the level shifter; a drain of the first field effect transistor M1 and a gate of the second field effect transistor M2 are connected to one terminal of the first capacitor C1; and the other terminal of the first capacitor C1 is connected to an input end of the phase inverter IVN, and a connecting end after the connection is used as a digital signal input end Vin; a gate of the first field effect transistor M1, a drain of the second field effect transistor M2, and a source of the third field effect transistor M3 are connected to one terminal of the second capacitor C2; and the other terminal of the second capacitor C2 and a source of the fourth field effect transistor M4 are connected to an output end of the phase inverter IVN; a power supply end of the phase inverter IVN is connected to the direct current power supply; a drain of the third field effect transistor M3 is connected to a drain of the fourth field effect transistor M4, and a connecting end after the connection is used as an analog signal output end Vout; and a gate of the third field effect transistor M3 and a gate of the fourth field effect transistor M4 may be connected to the direct current power supply.
In the level shifter shown in FIG. 1, because at the digital signal input end Vin, sometimes a digital signal “0” is input and sometimes a digital signal “1” is input, the first field effect transistor M1 sometimes is turned off and sometimes is turned on, to charge the first capacitor C1. Likewise, the second field effect transistor M2 sometimes is turned off and sometimes is turned on, to charge the second capacitor C2, so that a voltage difference exists between the two terminals of the first capacitor C1 and between the two terminals of the second capacitor C2, where the voltage difference is a direct current power supply voltage Vdd.
When a digital signal “0” is input at the digital signal input end Vin, a voltage corresponding to the digital signal “0” is 0. Potentials at points in the level shifter shown in FIG. 1 are shown in FIG. 2. A voltage of the input end of the phase inverter IVN is 0, and a voltage of the output end of the phase inverter IVN is Vdd. Because the voltage difference between the two terminals of the first capacitor C1 and the voltage difference between the two terminals of the second capacitor C2 cannot change suddenly, a voltage at the drain of the first field effect transistor M1, that is, a voltage at the gate of the second field effect transistor M2, is Vdd, and a voltage at the drain of the second field effect transistor M2 and at the source of the third field effect transistor M3, that is, a voltage at the gate of the first field effect transistor M1, is 2Vdd. According to the potentials at the points and types of the field effect transistors, states of the field effect transistors may be determined. Because the first field effect transistor M1 is an N-type field effect transistor, and the gate voltage 2Vdd is higher than the source voltage Vdd, the first field effect transistor M1 is turned on, and the first capacitor C1 is charged; because the second field effect transistor M2 is an N-type field effect transistor, and the gate voltage Vdd is not higher than the source voltage Vdd, the second field effect transistor M2 is turned off; because the third field effect transistor M3 is a P-type field effect transistor, and the gate voltage Vdd is lower than the source voltage 2Vdd, the third field effect transistor M3 is turned on; and because the fourth field effect transistor M4 is an N-type field effect transistor, and the gate voltage Vdd is not higher than the source voltage Vdd, the fourth field effect transistor M4 is turned off That is, when a digital signal “0” is input at the digital signal input end Vin, an output voltage of the analog signal output end Vout is 2Vdd.
When a digital signal “1” is input at the digital signal input end Vin, it is assumed that a voltage corresponding to the digital signal “1” is V0, and V0>0. Potentials at the points in the level shifter shown in FIG. 1 are shown in FIG. 3. A voltage of the input end of the phase inverter IVN is V0, and a voltage of the output end of the phase inverter IVN is 0. Because the voltage difference between the two terminals of the first capacitor C1 and the voltage difference between the two terminals of the second capacitor C2 cannot change suddenly, a voltage at the drain of the first field effect transistor M1, that is, the gate of the second field effect transistor M2, is Vdd+V0, and a voltage at the drain of the second field effect transistor M2 and at the source of the third field effect transistor M3, that is, the gate of the first field effect transistor M1, is Vdd. According to the potentials at the points and types of the field effect transistors, states of the field effect transistors may be determined. Because the first field effect transistor M1 is an N-type field effect transistor, and the gate voltage Vdd is not higher than the source voltage Vdd, the first field effect transistor M1 is turned off; because the second field effect transistor M2 is an N-type field effect transistor, and the gate voltage Vdd+V0 is higher than the source voltage Vdd, the second field effect transistor M2 is turned on, and the second capacitor C2 is charged; because the third field effect transistor M3 is a P-type field effect transistor, and the gate voltage Vdd is not lower than the source voltage Vdd, the third field effect transistor M3 is turned off; and because the fourth field effect transistor M4 is an N-type field effect transistor, and the gate voltage Vdd is higher than a source voltage 0, the fourth field effect transistor M4 is turned on. That is, when a digital signal “1” is input at the digital signal input end Vin, an output voltage of the analog signal output end Vout is 0.
It can be seen that, a minimum value of an output voltage of the level shifter in the prior art is 0. For some application scenarios in which there is a requirement that a minimum value of an output voltage of a level shifter is greater than 0, the level shifter shown in FIG. 1 obviously cannot meet the requirement, and therefore application scenarios of the level shifter are limited.